1. Field
Example embodiments relate to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a recess channel array transistor (RCAT) structure, in which a gate electrode includes a bridge-shaped inner spacer, and a method of manufacturing the same.
2. Description of the Related Art
As semiconductor memory devices are becoming more highly integrated, unit cell areas, line widths and intervals of patterns, and channel lengths are being reduced. Accordingly, leakage currents may increase due to short channel effects and large amounts of dopants being implanted into semiconductor substrates, which may reduce the refresh times of the semiconductor substrates.
A semiconductor device can be manufactured into a vertical gate structure and/or as a stacked gate structure to maintain electrical characteristics of the semiconductor device when a cell area is reduced. In addition, novel materials may be used for the gate structure of the semiconductor device to address the deterioration of the electric characteristics, in order to avoid modification of the gate structure.
A trench-type gate electrode has been utilized to increase the channel length at the gate electrode despite the cell area reduction. A recess channel array transistor (RCAT) structure, particularly, a spherical RCAT (SRCAT) structure, has been used as the trench-type gate electrode in a semiconductor device. In a conventional RCAT structure, a channel region of a gate electrode is usually recessed into a channel trench, and thus the channel length of the gate electrode can be sufficiently increased due to the increased surface area of the trench. Accordingly, the conventional RCAT structure may have a sufficient channel length despite the reduction of the cell area.
The conventional RCAT structure usually includes an inner spacer on an inner sidewall of the channel trench for reducing gate-induced drain leakage (GIDL). However, the above cell area reduction caused by the increase of integration degree may also reduce an available area for the inner spacer. The inner spacer for reducing the GIDL may be difficult to form on the inner sidewall of the channel trench, which may affect the GIDL in the conventional RCAT structure as the cell area is reduced.
According to the conventional RCAT structure, the channel trench can be formed on an active region of a substrate and a gate insulation layer can be formed along the inner sidewall of the channel trench. A lower portion of the gate structure can be formed in the channel trench and an upper portion of the gate structure can protrude from a surface of the substrate. An upper spacer can be formed on a sidewall of the upper portion of the gate electrode and an inner spacer can be formed between the lower portion of the gate electrode and the inner sidewall of the channel trench. Thus, the GIDL may be reduced at the gate electrode by the inner spacer.
There has been reported that the GIDL reduction is usually proportional to a depth and/or the width of the inner spacer. However, the increase of integration degree and the downsizing of the minimum feature size of a semiconductor device, for example, below about 4F2 (F: minimum feature size), may place various limitations on how much the depth and/or the width of the inner spacer can be increased, and thus the GIDL may be increased in the conventional RCAT structure as the cell area is reduced. Accordingly, the RCAT structure may be inappropriate for some semiconductor devices despite the various advantages of the conventional RCAT structure. In some cases, the RCAT structure may be completely replaced by a vertical pillar transistor (VPT) structure, and thus an RCAT structure may not be used in some semiconductor devices where the GIDL may not be sufficiently reduced.